1. Field of the Invention
The present invention relates to an input buffer circuit, and more particularly, to an improved input buffer circuit for stable operation of a memory cell.
2. Discussion of the Related Art
FIG. 1 illustrates the conventional input buffer circuit. The conventional input buffer circuit includes an address buffer 10 for buffering an input address ADDR, and an address signal generator 11 for generating an address transition detection signal ATD and internal address signals AN and ANB for a cell selection based on an output signal ANIB from the address buffer 10.
FIG. 2 illustrates the input buffer circuit. The input buffer circuit includes a NOR-gate NR1 for NORing an input address ADDR and a chip selection signal CSB, inverters I1 and I2 for sequentially inverting output signals from the NOR-gate NR1 and outputting an address signal ANIB, and a PMOS transistor PM1 connected between a power supply voltage VCC terminal and an output terminal of the NOR-gate NR1.
The address signal generator 11 includes inverters I3 and I4 for inverting the output signal ANIB from the address buffer 10 and outputting an address transition detection signal ATD and an internal address signal AN, and inverters I5 and I6 for sequentially inverting the output signal from the address buffer 10 and outputting an internal address signal ANB.
The operation of the conventional input buffer circuit will now be explained with reference to the accompanying drawings.
When the chip is enabled by a LOW chip selection signal CSB as shown in FIG. 3A, the address buffer 10 sequentially inverts the input address ADDR, as shown in FIG. 3B, and outputs an address signal ANIB. The address signal generator 11 inverts the address signal ANIB and outputs the address transition signal ATD and address signals AN and ANB, as shown in FIGS. 3C and 3D.
In addition, the decoder 12 is driven by the address signals AN and ANB and outputs address signals OUT1 and OUT2 as shown in FIGS. 3E and 3F, so that data is outputted from a memory cell 13.
The output signal of the NOR-gate NR1 is frequently in a noise margin range around a transition voltage between the voltage VIL, where an input signal is recognized as LOW, and the voltage VIH, where the input signal is recognized as HIGH.
As a result, around the transition voltage, the NOR-gate NR1 does not output a well-defined output value due to the noise, and outputs of the inverters I1 and I2 become unstable due to the unstable output of the NOR-gate NR1.
In addition, as shown in FIGS. 3C and 3D, the internal address signals AN and ANB become HIGH due to the unstable output ANIB of the inverter I2. When the internal address signals AN and ANB become HIGH, the memory cell 13 is selected, and data in the memory cell 13 may be lost.
Therefore, around the transition voltage, the pull-up PMOS transistor PM1 is added for pulling up the input voltage from the inverter I1 as shown in FIG. 2 in order to stabilize the output of the NOR-gate NR1.
However, a hysteresis effect occurs between an input voltage Vin and an output voltage Vout of the inverter I1 due to the addition of the PMOS transistor PM1, so that the output voltage Vout from the inverter I1 exhibits a characteristic degradation by .DELTA.V.